1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements that comprise a high-k metal gate electrode structure formed in an early process stage.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a very high number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Currently, a plurality of process technologies are practiced, wherein, for many types of complex circuitry including field effect transistors, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
A significant gain in performance of advanced semiconductor devices has been achieved by continuously reducing the lateral dimensions of the individual circuit elements, such as the field effect transistors. To this end, the gate electrode is generally a very critical circuit feature of the field effect transistor, which basically determines the overall transistor characteristics and also the drive current capability. For example, switching speed and current drive capability of the channel may be increased by reducing the channel length and/or by increasing the charge carrier mobility in the channel region, which may be accomplished, in most recent developments, by inducing a certain type of strain in the channel region. On the other hand, the approach of reducing the channel length has been followed over the last decades, thereby resulting in a channel length of less than 50 nm in most recent field effect transistors used in sophisticated circuits, such as CPUs and the like. Consequently, the length of the gate electrode structures of similar dimensions requires very sophisticated patterning strategies, wherein typically, in view of superior alignment of the gate electrode structure and the channel region, the gate electrode structure is formed prior to performing any implantation processes for introducing the dopant species for the drain and source regions. Upon further reducing the overall dimensions of complex transistor elements, it turns out that very sophisticated dopant profiles are required in the vicinity of the channel region in order to provide superior conductivity of the drain and source regions, while at the same time appropriately configuring the electrical field distribution in the vicinity of the channel region. Moreover, the overall dopant concentration at and within the channel region also significantly determines transistor specific characteristics, such as threshold voltage, i.e., the voltage at which a conductive channel forms in the channel region, so that corresponding complex implantation sequences have to be performed for N-channel transistors and P-channel transistors, respectively, while using the respective gate electrode structures as efficient implantation masks. For example, in sophisticated field effect transistors, typically so-called drain and source extension regions, i.e., extremely shallow doped regions with a moderately high dopant concentration, have to be provided which may connect to the channel region, thereby substantially defining the effective channel length of the transistor. On the other hand, underlying drain and source areas have to be provided with a reduced lateral offset from the channel region, however, with high dopant concentration and with a depth that may also significantly influence the overall transistor characteristics. Moreover, complex counter-doped areas may have to be provided in the remaining body region of the transistor, thereby obtaining PN junctions with increased dopant concentration gradients, which may result in superior transistor performance. Such counter-doped regions, i.e., counter-doped with respect to the drain and source doping, may also be referred to as halo regions and typically require complex tilting implantation process techniques in order to position the counter-dopants below the gate electrode structure at an appropriate depth within the active region.
Due to the complex implantation process sequence for implementing the drain and source dopant species and the counter-doping species, the lateral masking effect of the gate electrode structure may have to be appropriately adapted, for instance, with respect to the drain and source extension regions and halo regions, to the deep drain and source areas and the like, which may be accomplished by providing an appropriate spacer structure having a different lateral width at the various manufacturing stages. That is, for incorporating the drain and source extension dopant species, which have to be positioned laterally adjacent to the channel region, a spacer structure or spacer element with reduced width is to be used, while incorporating the dopant species for the deeper drain and source areas, a spacer structure of increased width has to be applied. Typically, spacer elements are provided by depositing an appropriate material, such as silicon nitride, by using conformal deposition techniques followed by an appropriate etch process, typically performed as anisotropic plasma-based etch processes, thereby preserving a portion of the previously deposited spacer layer at the sidewalls of the gate electrode structures, which may thus act in combination with the gate electrode structure as an efficient implantation mask. Typically, also any etch stop liners, such as a silicon dioxide material, may be used in combination with the actual spacer material in order to provide superior conditions and thus controllability of the process of forming sidewall spacers. Upon further reducing the overall dimensions of the transistors, the spacer structures may have to be adapted to the required lateral and vertical dopant profiles of the drain and source regions, thereby also requiring superior controllability of any process strategies for forming the spacer structure.
It turns out, however, that any patterning-related non-uniformities, which may be induced in the gate electrode structure during the complex patterning process, and also any process non-uniformities upon depositing and patterning a spacer material may increasingly affect the transistor characteristics when, for instance, the gate length is continuously reduced. For example, a variation in width of a spacer structure of several nanometers may not unduly affect the characteristics of a transistor having a gate length of 100 nm and more. On the other hand, a variance of the spacer width in this order of magnitude may have a significant influence on the finally obtained lateral and vertical dopant profile in transistors having a gate length of 50 nm and significantly less, thereby also inducing a corresponding variability in the finally achieved transistor characteristics. Furthermore, due to the complex patterning process for forming gate electrode structures in the corresponding spacer elements, typically the process flow is designed such that gate electrode structures and corresponding spacers are provided commonly for P-channel transistors and N-channel transistors, wherein the selective incorporation of the appropriate dopant species is accomplished by using appropriate masking regimes on the basis of resist masks formed by lithography techniques. Thus, upon incorporating a P-type dopant species for a P-channel transistor, the corresponding N-channel transistors may be masked, while the implantation parameters may be specifically selected so as to take into consideration the desired vertical and lateral dopant profile for the P-channel transistor, wherein also the masking effect of the gate electrode structure and the spacer structure is taken account of. Thereafter, a corresponding mask is provided so as to cover the P-channel transistors and appropriate implantation parameters are selected for achieving the desired transistor characteristics of the N-channel transistors.
It turns out that, although basically the gate electrode structures of the P-channel transistors and the N-channel transistors may have experienced the same process flow, small variations may be introduced, for instance with respect to spacer width, which may thus affect the further processing, for instance in terms of incorporating appropriate dopant species. For example, in sophisticated patterning strategies, it has been observed that, for instance, the spacer width of P-channel transistors may be less compared to the spacer width of N-channel transistors, which may, however, require a corresponding initial design of the spacer structures such that a required minimum spacer width is provided for the P-channel transistors, since here typically boron is used as the dopant species which exhibits a pronounced diffusion activity compared to N-type dopant species, such as arsenic and the like. Consequently, for a given transistor architecture and a specific thermal budget during the anneal processes for activating the dopant species, the spacer width has to ensure a required minimum offset from the channel region or the gate electrode structure in view of the incorporation of the boron species. In this case, the spacer width of the gate electrode structures of the N-channel transistors may further be increased, which on the other hand may also result in a reduced exposed area for incorporating the N-type dopant species in transistor areas in which closely spaced gate electrode structures have to be provided. In this case, for example, the gate electrode structures of closely spaced N-channel transistors may have a reduced lateral offset or spacing between the corresponding spacer structures, thereby also reducing the surface area that is available for incorporating the N-type dopant species, which may result in a reduced dose, thereby also affecting the finally obtained transistor characteristics. For example, the reduced dose incorporated during the complex implantation process may result in a reduced or missing dopant concentration at the bottom of active regions, which may specifically influence the transistor characteristics in a silicon-on-insulator (SOI) architecture in which the parasitic capacitance of the PN junctions may significantly depend on the fact that deep drain and source areas may have to connect to the buried insulating material layer.
As discussed above, performance of sophisticated transistors may not only be increased by reducing the gate length, but also other mechanisms may be implemented, for instance in view of increasing the charge carrier mobility and/or improving the electronic characteristics of the gate electrode structure for a given geometric configuration thereof. For example, with respect to the former aspect, frequently strain-inducing mechanisms may be implemented into the overall process flow for forming sophisticated transistors, wherein one very promising approach is the incorporation of a strain-inducing silicon/germanium material into the drain and source areas of the P-channel transistors. The silicon/germanium alloy may typically be formed on the basis of appropriate selective epitaxial growth processes, thereby achieving a highly strained state, which in turn may result in a compressive strain, which may increase the hole mobility. The silicon/germanium material is typically incorporated after patterning the basic gate electrode structure by forming respective cavities in the active region and refilling the cavities with the silicon/germanium material.
The latter aspect for enhancing transistor performance by improving the electronic characteristics of the gate electrode structure may be realized by using superior dielectric material, which provides a desired high capacitive coupling while not unduly increasing the gate leakage currents. To this end, so-called high-k dielectric material may be incorporated into the gate insulation layers, wherein a high-k dielectric material is to be understood as a dielectric material having a dielectric constant of 10.0 or higher. Moreover, in these approaches, typically a metal-containing electrode material may be incorporated in the vicinity of the gate dielectric material in order to avoid the presence of the typically used polysilicon material, since this material typically forms depletion zones upon operating the transistor device.
Consequently, in any of these sophisticated process strategies, generally the complexity of the gate patterning process and any subsequent processes may have an influence on the further processing and thus on the finally obtained sidewall spacer structures, which in turn may result in a certain variability of the drain and source regions formed by implantation processes, as is also discussed above. For example, generally the process of incorporating a strain-inducing semiconductor alloy in the drain and source regions of one of the transistors may result in a sophisticated device topography, which in turn may affect the subsequent lithography processes and patterning processes, which in turn may result in small differences of the resulting gate electrode structures. Similarly, the patterning process of the gate electrode structures may be a complex sequence of lithography and etch steps, wherein typically sacrificial material systems may have to be provided, such as hard mask materials, in order to form the gate electrode structures with the desired gate length and gate width. To this end, frequently a material layer or layer system, for instance mainly comprised of silicon nitride, may be used, wherein this material may further be maintained, for instance throughout the fabrication process for providing the strain-inducing semiconductor alloy in one of the transistors so that this dielectric cap material or hard mask material may experience different process conditions in different transistor types. Moreover, this cap material has to be removed during the further processing of the semiconductor device, which is also typically accomplished by providing a sacrificial spacer structure, which may allow the removal of the dielectric cap layer, however, without unduly affecting any remaining components of the gate electrode structures, such as the very sensitive high-k dielectric materials and any metal-containing electrode materials, which are reliably confined by an appropriate sidewall spacer structure, which, however, would unduly be affected by the cap removal process.
As is evident from the above description, the process of patterning gate electrode structures and the corresponding spacer structures may involve a plurality of very complex interrelated process steps so that, for instance, the individual provision of spacer elements for N-channel transistors and P-channel transistors may additionally increase the overall complexity of the patterning process. On the other hand, spacer width variability, for instance between N-channel transistors and P-channel transistors, may significantly affect the overall transistor characteristics, in particular in sophisticated semiconductor devices in which additional performance enhancing mechanisms are implemented.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.